Embodiments of the present invention relate generally to semiconductor devices, and more particularly, to semiconductor devices having a striped orientation of trenches and contact windows.
Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated herein by reference.
Superjunction devices, including, but not limited to metal-oxide-semiconductor field-effect transistors (MOSFET), diodes, and insulated-gate bipolar transistors (IGBT), have been or will be employed in various applications such as automobile electrical systems, power supplies, and power management applications. For example, superjunction devices may specifically be employed in light emitting diode (LED) televisions, electric or hybrid cars, LED light bulbs, servers, tablets, uninterruptable power supplies (UPS), and the like. Such devices sustain high voltages in the off-state and yield low voltages and high saturation current densities in the on-state.
FIGS. 1 and 2 show a conventional arrangement for a semiconductor device 10. A semiconductor substrate 12 supports a semiconductor layer 14 with a plurality of trenches 16 formed in a first main surface 14a of the semiconductor layer 14. First and second doped regions 18, 20, typically source/drain and body contact regions, respectively, are formed proximate the first main surface 14a. A layer of dielectric material 22 is formed over the first main surface 14a of the semiconductor layer 14 which isolates a gate 24 from the semiconductor layer 14. A plurality of contact windows 26 are formed in the dielectric layer 22 to expose the first and second doped regions 18, 20 such that a later formed metal contact 28 can be electrically and preferably physically coupled to the first and second doped regions 18, 20. In this conventional structure, as best seen in FIG. 1, the trenches 16 are arranged in a grid pattern of rows and columns. Closely surrounding a periphery of each trench 16 is a cluster of contact windows 26.
It is desirable to provide a semiconductor device with reduced cell sizes and higher cell densities, a lower on-resistance, and a lower gate charge.